Data from DDR SDRAM memory typically arrives at the inputs of a receiving device both on the rising and falling edges of a clock, along with a phase-shifted strobe signal. Such a strobe begins with a logical low signal level for one memory clock period called the preamble, and a predetermined number of tandem rising and falling edges occur followed by a half-clock period postamble that is also a logical low signal. The strobe then enters an undefined (tristate) phase. The strobe's rising and falling edges between the preamble and postamble are deterministically centered in the data windows of the received data.
The strobe must be enabled during the preamble phase and not before to prevent capturing noise or other false data as received memory data, and must also be enabled in time to ensure the first rising edge corresponds to arrival of the first data symbol to properly capture the arriving data. Because the data from the DDR SDRAM is provided from memory that is often operating at a very high clock rate and that is not physically proximate to the memory controller, read loop delay can be substantial. Factors comprising or contributing to read loop delay include silicon or propagation delay in communicating data from silicon devices to the interconnect level, interconnect propagation delay between the memory semiconductor to the memory controller, PLL jitter, DRAM DLL uncertainty, and other factors. Delay can also be affected by the number of DIMMs per memory channel in large systems, and by physical factors such as silicon process, interconnect design, voltage, temperature, etc. These factors can cause the read loop delays to exceed one clock cycle, and in some cases can also cause the difference between minimum and maximum read loop delays in a system to exceed a full clock cycle.
Because DDR SDRAM strobes are undefined during certain phases before and after data bursts and because the read loop delay can exceed one clock period, data synchronization with the memory controller can become difficult. This problem becomes increasingly important as faster memory is utilized, especially with DDR SDRAM memory channels that are fully populated with four DIMMs per channel.
Solutions have included placing all DDR SDRAM memory physically close to the memory controller, which typically is also near the processor bus and other data channels and so must compete for space. Alternatively, memory can be located away from the memory controller, with additional PCB trace padding for memory that is nearer the controller to ensure that all memory read loop delays are within one clock cycle of each other. But, this solution requires additional substantial PCB traces, which again is expensive and makes circuit board layout complex and inefficient. More common is simply limiting the window between maximum and minimum read loop delays to a single clock cycle by reducing the DIMM count per channel, limiting memory clock frequency, or limiting the number of memory channels per memory controller device.